Non-linear decoder



May 5, 1970.

Filed Sept. 8, 1966 Fig.1 (0) Fig.1(d)

A. E. J. CHATELON 3,510,868

NON-LINEAR DECODER 5 Sheets-Sheet 1 Fig.1(b) Y Fig/1(0) Fi .1(e)

Fig.1(f)

I inventor ANDRE E. J. CHATELON May 5, 1970 A. E. J. CHATELON NON-LINEARDECODER Filed Sept. 8. 1966 5 Sheets-Sheet 2Illlulllil'llilll'lll'lllll'lll-llllllllii.

I n ventor ANDRE 6. J. (f/A TLON KQSW R United States Patent 3 ,5 Int.Cl. H03k 13/04 US. Cl. 340347 7 Claims ABSTRACT OF THE DISCLOSURE Anon-linear PCM decoder wherein the digits of a code group to be decodedare first stored in stages of a register. A preliminary decoder iscoupled to the stages of the register storing the x most significantweight digits of the code group to provide a first control signalindicating the straight line segments of the input-output characteristicwhich are represented by the stored code group. A first signal generatorcoupled to the preliminary decoder and the stages of the registerstoring the most significant weight digits of the code group acts toproduce a second control signal indicating the lowest voltage of thesegments. A second signal generator operated responsive to said firstcontrol signals and the stages of the register storing the m leastsignificant weight digits of the code group to produce a third controlsignal indicating a position along the segment indicated by the secondcontrol signal. A ladder attenuator and current generators are providedwhich respond to the second and third control signals to produce theanalog signal represented by the stored code group at the output of theattenuator.

The present invention concerns a non-linear decoder for convertingbinary numbers into analog quantities.

Such non-linear digital to analog decoder may be used on the one hand asa decoder-expanser and on the other hand as a decoder associated to acoder-compressor, the coding being carried out by the feedbackcomparison method.

Feedback coding consists in comparing the analog value representing anumber stored in a register to the signal to be coded, thus enabling todetermine whether the number is too big or too small. In the first case,this number is reduced, in the second case, it is increased. Thesecomparison operations are carried out up to the time when the voltagescompared do not differ at the most by the value of one quantizationstep.

When the used decoder is not linear, the coding is carried out accordingto a non-linear characteristic curve. Since the same decoder may be usedfor coding and for decoding, the compression and expansioncharacteristics are then perfectly complementary if said decoderpresents reproducible characteristics.

Non-linear decoders which make use of a resistance network and whichenable to obtain an hyperbolic characteristic are known. Theseresistances, the extreme values of which are in the ratio 2, must beswitched in accordance with the value of the number to be decoded. Butit is known that any resistance presents a certain reactance whichdepends upon its value. If the switching frequency is high, the effectof this reactance becomes important, and the value of the correspondingcomplex impedance depends upon the number to be decoded. It is thusrealized that a decoder which comprises resistances having suchdifferent values is difficult to achieve and cannot provide a highaccuracy. Besides, when an electronic switch is used for sampling thesignal to be coded, the said switch pre- 3,510,868 Patented May 5, 1970sents, when it is conducting, a series resistance (saturation resistancein the case of a transistor) which is not negligible in respect to thesmall value resistances of the network, and which introduces a newsource of errors.

To overcome the difiiculties of obtaining a continuous non-linearcharacteristic, the U8. Pat. No. 3,298,017 entitled Non-Linear Decoder,which issued Jan. 10, 1967 and is assigned to the assignee of thisinvention, has described a decoder achieved in such a way that itscharacteristic curve is constituted by a series of straight linesegments of different slopes; these slopes can be chosen in such a wayas to be, for instance, approximately tangent to a logarithmic curve.

The operation of this decoder will be briefly reviewed by recalling anexample wherein the numbers or codes which are applied to it comprisen=7 digits, and that the voltages corresponding to the zero and to 2codes are equal respectively to zero and Ed, the codes 2 -1 and 2 beinglocated on both sides of the voltage Ed/2 which characterizes the meanvalue of the signal in the case where the codes represent alternatingvoltages. Each one of these voltage ranges of amplitude Ed/Z is dividedinto three coding zones C1, C2, C3, to which correspond, respectively,32, 16 and 16 codes, and in which the values of the quantization stepsare different. Thus, in the zone C1 which corresponds to the lowestvoltages in absolute value on both sides of the origin, the value ofthis step is equal to V. In the zone C2, it is equal to 8 v., and in thezone C3, it is equal to 64 v. A characteristic curve is thus defined,constituted by six segments, the slopes of which are proportional to thedifferent values of the quantization steps.

In order to obtain the analog voltage corresponding to a given code, thezone to which it belongs is first determined, this operation beingcarried out easily by decoding a group of its more significant digits,for example, its four more significant digits, since each zone comprisesa number of codes equal to an integral power of two. The zone signalthus obtained is used on the one hand for elaborating a base voltage orpedestal equal to the voltage which corresponds to the maximum code ofthe immediately preceding zone, and on the other hand, a complementaryvoltage representing the position of the code in the zone to which itbelongs; this voltage being obtained by decoding linearly the lesssignificative digits with a weighting corresponding to the value of thequantization step in the zone. These two voltages are then added inorder to obtain the analog voltage corresponding to the code.

In a transmission system using this circuit, for feedback coding and fordecoding, a substantial increase of the distortion level is observed atthe connection between the adjacent zones. Obviously, the distortion isthe more important as the ratios between the consecutive slopes of thecompression curve are higher, i.e. when the number of zones is smaller.

In order to take full advantage of the compression, it is thus necessaryto smooth the characteristic curve, i.e. to increase the number ofslopes. It will be noted that if it is required to set up anon-continuous characteristic curve in which the ratios between theconsecutive slopes are all equal, the envelope of this curve is a truelogarithmic function.

The object of the present invention is thus to realize a non-lineardecoder with a non-continuous characteristic which yields low distortionvalues when used for the feedback coding, and for the decoding of lowfrequency signals.

The present invention will be particularly described with reference tothe accompanying drawings in which:

FIG. 1 represents a certain number of symbols used in FIG. 3,

FIG. 2 represents the characteristic curve of the decoder according tothe invention,

FIG. 3 represents the detailed diagram of this decoder,

FIG. 4 represents the same characteristic curve as that of FIG. 2 usinga non-linear scale on the abscissae axis,

FIG. 5 represents the elaboration circuit of the control signals of thecomplementary voltages.

Before starting the description of the invention, one will brieflyremind the principle of notations in logical algebra which will be usedin certain cases, in order to simplify the writing in the description ofthe logical operations. The subject is treated extensively in numerouspapers and in particular in the book Logical Design of Digital Computersby M. Phister (J. Wileypublisher).

Thus, if a condition characterized by the presence of a signal iswritten A, the condition characterized by the absence of said signalwill be written K. These two conditions are linked by the well knownlogical relation A Z=0, in which the sign X is the symbol of thecoincidence logical function or AND function.

If a condition C appears only if the conditions A and B aresimultaneously present, one writes A B=C and this function may becarried out by means of a coincidence or AND circuit.

If a condition C appears when at least one of two conditions E and F ispresent, one writes E+F=C and this function is carried out by means of amixing gate or OR circuit.

Since these AND and OR logical functions are commutative, associativeand distributive, one may write:

Last, a function of two variables A andB may present four possiblecombinations and, if one writes A B,the three other combinations areglobally represented by the expression AXB.

One will also specifiy, in relation with the FIG. 1, the meaning of someparticular symbols used in the drawings which come with the descriptionof the invention. Thus:

FIG. 1a represents a simple AND circuit,

FIG. 1b represents a simple OR circuit,

FIG. represents a bistable circuit or flip-flop to which a controlsignal is applied over one of its input terminals 92-1 or 92-0 in orderto set it in the 1 state or to reset it in the 0 state. A voltage ofsame polarity as that of the control signal is present, either on theoutput 93-1 when the flip-flop is in the 1 state, or on the output 93-0when it is in the 0 state. If the flip-flop is referenced B1, thelogical condition which characterizes the fact that it is in the 1 statewill be written B1 and that characterizing the fact that it is in the 0state will be Written F1,

FIG. 1d represents a group of several conductors, ten in the consideredexample,

FIG. 1e represents a decoder which, in the case of the example,transforms a four-digit binary code group applied over the group ofconductors 94a into a 1 out of 16 codes, so that a signal appears ononly one among the sixteen conductors 94b for each one of the codegroups applied at the input,

FIG. 1 represents a current generator supplied by a voltage source +V.This generator, which is triggered by a control signal applied to itsinput terminal 940, delivers a constant current of amplitude I in theresistor R of very low value compared to the internal impedance of saidgenerator.

The generators shown on FIG. 3 are not referenced but one understandsthat they can be referenced unambiguously by their control signals.

One will characterize by a particular expression the position of a givendigit in a binary code group and, by extension, the position of theflip-flop, in a counter or a register, which stores said digit. One willthus say that the most significant digit of a code group is the digit ofrank 1, the next significant digit being then the digit of rank 2, etc.One will note that this notation is independent from the utilized codewhich may be weighted or not.

The FIG. 2 represents the characteristic curve e=f(N) of the decoderaccording to the invention, designed to make correspond to N codescomprising at least four digits, voltages the average value of which, inthe case of sinusoidal voltages, is equal to Ed/ 2 and the peakamplitude of which is equal to The codes formed by the four mostsignificant digits have been shown between parentheses on the ordinateaxis NIN, and the range of decoded voltages which extends from zero voltto Ed has been represented on the abscissae axis OIe.

This characteristic curve is discontinuous as it is constituted by asuccession of straight line segments of different slopes. It issymmetrical with respect to the point I and presents, in each one of thefirst and third quadrants, seven coding zones, the ratios between theslopes of the adjacent zones in each one of these quadrants being equalto 2, as it may be seen from Table I hereafter. In this table, thecolumn 1 is assigned to the zones C1 to C7, the column 2 to the slope ineach one of these zones (in volts per code), the column 3 to the numberof codes per zone, the column 4 to the number of unit quantization stepsV in each zone, and the column 5 to the fraction of the voltage rangeEd/ 2 occupied by each zone.

On FIG. 2, the coding zones concerning the codes of which the digit ofrank 1 is 0 have been referenced C1 to O7, and those concerning thecodes for which this digit is 1 have referenced C"1 to C7. Since thecharacteristic curve is symmetrical with respect to the origin I of thecoordinates, it is understood that the zone 01, for instance, of theTable I corresponds to the zones U1 and C"1 of FIG. 2. The constructionof the characteristic curve in each one of the quadrants it occupies maybe easily deduced from the indications given in the column 5 of Table I.

TABLE I Number of quantizing Number of steps in Fraction codes the zoneof Ed/2 Norm-Total number of quantizing steps=1,024.

FIG. 3 represents the general diagram of the decoder according to theinvention which comprises: the register RG comprising the flip-flops B1to B7 for the storage of codes comprising n=7 digits, the zone decoderZD, the generator of pedestal signals PC, the generator of complementarysignals LD, and the averaging and summation circuit WR which supplies,on its output X, a voltage characterizing the value of the codestored inthe register RG.

The outputs of the flip-flops B1 to B4 are applied to the zone decoderwhich comprises the twenty-one following outputs:

G1 to O7 and C"1 to C7 characterizing the zones defined by the digits ofrank 1 to 4 represented on FIG. 2,

C1 to C7 characterizing the homologous zones of the two parts of thecharacteristic curve such as they are defined in column 1 of Table I.

The role of the generators PC and LD is to supply to the circuit WRcontrol signals which characterize, re-

spectively, the decoded minimum voltage of each coding zone, and thecode position in the zone.

The averaging and summation circuit WR comprises a ladder attenuatorsupplied by current generators the type of operation of which, wellknown in itself, has been described in the patent mentioned hereabove.

Since the terminating shunt resistors of this attenuator have a value R,by choosing values 2R and R respectively for the other shunt and seriesresistors, an attenuator is obtained having a characteristic impedance2R/3 which brings an attenuation of two per cell.

It results therefrom that if a current I is injected at the point Q0, avoltage appears between the point X and ground, and that, if theinjection point is moved towards the left of the figure, the voltage Vxdecreases each time by a ratio of two. It is 6 C6 and to the value ofthe quantization step of this zone are added to this voltage U'o.

At each zone change, the operation is carried out in a similar way, atleast up to the zone C1 the pedestal of which is constituted by the sumof the voltages U'o, U'l, U2, U'3, U4, U'S, respectively equal to 512v., 256 v., 128 v., 64 v., 32 v. and 16 v.

Table II hereafter represents the different pedestal voltages used. Itcomprises the lines 1, 2, 3, reserved respectively to the value-given inquantization unit stepsof the voltage, to the reference of the voltages,and to the reference of the current generator set into operation in thecircuit WR.

This table comprises also the columns a and b assigned respectively tothe fourteen coding zones and to the four most significant digits of thecodes which characterize said zones.

In this table, the generators set into operation for the ditferent zonesare represented by crosses located at the cross-points of thecorresponding columns and lines.

TABLE I1 1 Weightin 512 256 12s 64 32 1e 32 64 12s 256 512 2 Zone l Zdecoding UO Ul W2 W3 U4 u's U"4 U3 U2 U1 U0 one a B1 B2 B3 B4 PO Pl P2P3 P4 P'5 1 4 P3 P2 P1 P0 o 0 0 0 0 1 X o 1 0 X X 0 1 1 X X 1 0 0 X X 1a (1 X 1 1 1 X X 0 0 1} X X o 1 0 X X 0 1 1 X X 1 0 o X X 1 0 1 X X 1 10 X X 1 1 1 X X X thus seen that the attenuation ratio is a negativepower of two, the exponent of which is given by the digit associated tothe reference letter of the injection point. Thus, a current injected atpoint Q2 generates a voltage attenuated by the ratio 2F A with respectto the same current injected at the point Q0.

Besides, if currents supplied by two identical generators of highinternal resistance with respect to the characteristic impedance areinjected in a given point, the currents add and the output voltage isdoubled.

The method used for the choice of the pedestal voltages will be firststudied, in relation with FIG. 4. This figure represents the samecharacteristic curve as that of FIG. 2, but it is set up by using anon-linear scale on the abscissae axis. The abscissae valuescorresponding to the zone changes are shown between brackets, and it isseen that the scale used enables to assign the same length, on

the abscissae axis, for each coding zone.

The decoding voltages corresponding to the codes of the zone 07 rangebetween zero volt for the code the decimal equivalence of which is zero,and

for the code the decimal equivalence of which is 7. These arecomplementary voltages elaborated as it will be seen further on underthe control of the signal supplied by the circuit LD.

As it has been seen previously, the pedestal for the zone 01 isconstituted by the sum of the voltages UO to U'5.

In order to obtain the pedestal of the next zone C"-1, a voltage ofamplitude equal to 16 v. may be added to the pedestal of the zone C1 andso on, until thirteen added voltages are obtained for the zone C"7.Nevertheless, the number of components used would thus be increaseduselessly. Since it is required mainly to keep a relative constantaccuracy, the pedestal voltages for the zones C"1 to C"7 are chosen in aparticular way.

Thus, the pedestal of the zone C1 is obtained by adding the voltages UOto U4 plus a voltage U"4 of amplitude 32 v. The other pedestals used forthe zones C"2 to C"7 are obtained in a similar way as it may be seen inTable II and FIG. 4. This last figure has been drawn in order to showhow the pedestal voltages add up and if one examines, for instance, thedotted line ending at the reference C"4 written in the column C at theleft of the figure, one sees that the pedestal for this zone is obtainedby adding the voltages U'O, U'l, U2, U3 and U"2.

The circuit PC supplies, in accordance with the indications given inTable II, a certain number of signals for the control of the generatorsin the circuit WR.

The logical conditions of elaboration of these signals are deducedimmediately from Table II. Thus, it is seen that the signal P'0, usedfor triggering the generator hearing the same reference, must appearwhen at least one of the flip-flops B1 to B4 is in the 1 state, viz.:

In the same way, the signal P 8 The Table III hereafter gives the wholeof the logical elaboration of signals of control of complementaryvoltconditions set up in the generator PC. ages.

TABLE In FIG. represents a part of the circuit LD which receives thesignals C1 to C7, B4 to B7, and which com- Control signal: Logicalconditions prises twenty-two AND circuits in a matrix arrangement P5aC'1+C2 and which supplies the twenty-two output signals repre- P4C1+C2+C"3+C"7 sented on the right side of the figure. P4a C"7+C"1+C"2 Inorder to simplify the figure, the AND circuits have P'3 P4-l-P'3a(P'3a=C'3+C"4 not been referenced, though it is realized that they carryP"3a C"3 10 the same references as the output signals. PZ P'3+C'4+C"'5The digits associated to the reference F of the output P"2a C4 signalshave an accurate meaning: thus, the first digit, P'l B2+B3+B4 from 1 to7, characterizes the zone for which this signal P"1a C"'5 appears, andthe second digit, from 4 to 7, characterizes P'tl B1+B2+B3+B4 the rankof the flip-flop which has controlled the genera- P0 C6+C"7 tion of thesignal when setting in the 1 state. When a reference such as P5 isfollowed by an index Thus in the Zone the eohdihon B5XBQXB7 a or b, thismeans that the generator P5 may be controlled, (cede 211-1) does notcontrol the generation of y 5181131,

through an OR circuit, either by a signal P5a or by a the condition X X(Code E the signal PSb, this signal being supplied by a circuit LD thegeneration of the signal F17, the condition B5 B6 B7 operation of whichwill be studied now. induces the generation of the signal F16, etc.

' TABLE IV 5 Injection Point Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q Q Weighting As ithas been seen previously, the role of this circuit Table IV presents aclassification of these signals F in is to supply to the circuit WRcontrol signals for the cur accordance with the zones to which belongthe codes, and rent generators, in order to elaborate a complementarywith the current injection points controlled by these sigvoltage whichcharacterizes the code position in the zone, 40 nals. The last linecarries the reference of the control this voltage being added-in theladder attenuator-to the signal elaborated by the mixing, in the ORcircuits, of the pedestal voltage. signals F carried in a same column,these OR circuits be- For the zone C"1, the value of the quantizationstep ing placed in the circuit LD.

is V, and it will be noted that the complementary voltage One has thus,for instance:

is obtained by the decoding of the flip-flops B4 to B7,

since this zone comprises sixteen codes whereas the com- P9=F17plementary voltage related to the other zones which com- P8=Fl6+F27prises only eight codes is supplied by the decoding of the 7=F15+FZG+F 7flip-flops B5 to B7. In this zone C1, the code 2 (logical condition:BZXEXBTXBT) controls the generation of the pedestal voltage UO-l-U'4+U"4. The next The control signals shown in the left side column ofcode 2 +1 (logical condition: B IXKEXE 'B Z) m t Table III and in thelowest line of Table IV are applied, control the elaboration of acomplementary voltage V, in the Circuit WR t0 the control inputs of thethat the code 2 +2, the elaboration of a complementary currentgenerators. Two generators are connected to each voltage 2 v., etc.Since one of the points Q0, Q1, Q2, Q3, Q4, the first one of these beingcontrolled by a signal Whose reference is fol- V lowed by the sign andthe second by a signal whose =2- reference is followed by the signBesides, some of these generators are controlled by a two-input ORcircuit. 0 This case occurs when two signals written in the Tables the h2n 1+1 will trigger the e 'e connected to III and IV bear, on the onehand, the same reference the point, P9, the code 2 +2 will trigger agene digit-this meaning that they control the injection of a connectedto the Pomt current at the same point of the attenuator-and on the Inthe h clz h Va h1e Pi unit Step is 2 50 other hand, 'difierent smallletters a and b. It will be that the logleal cohdltloll B5 X X controlsthe elaho- 5 noticed in fact that these two signals cannot appearsimulrition of a complementary voltage 2 the condition taneously: thus,the signal P3a is elaborated for the B5 |B6 B7 the elaboration of avoltage 4 v., etc zone C"3, and the signal P"3b is elaborated for one ofAs the zones C5, C6, C7.

2V It has been shown, in the patent mentioned hereabove,

=2- that if the last generator set into operation was replaced,

at the passage from the zone Cl to the zone C1, by a generator connectedto an injection point of lower index, the first one of these conditionswill trigger a generator an amplitude distortion of the decoding signaltakes place connected to the point P8, etc. together with anamplification of the noise. Thus, in the FIG. 5 and Table IV hereafterconcern the mode of decoder just described, the generator P5 is replacedby TABLE V Control signal: Logical conditions Pa C1+C"2 P ls Clll P'4C1+C2+C3+C"7 P"4a C"2+C7 While the principles of the above inventionhave been described in connection with specific embodiments andparticular modifications thereof it is to be clearly understood thatthis description is made by way of example and not as a limitation ofthe scope of the invention.

' I claim: a

1. A non-linear decoder for translating n-digit binary code groups intovoltages represented thereby having a non-linear code group input vs.voltage output characteristic formed from a plurality of successivestraight line segments each having a different slope and extending froma different lower value of voltage to a difierent higher value ofvoltage comprising: register means for storing the digits of each ofsaid code groups; zone decoder means coupled to said register means andoperated responsive to the x most significant weight digits of a storedcode group to produce zone control signals indicating the segments ofsaid characteristic represented by said stored code group, where x is aninteger less than n; pedestal signal generator means coupled to saidregister means and said zone decoder means for providing first controlsignals indicating the lower value of the voltage of the segments;complementary signal generator means coupled to said register means andsaid zone decoder means operated responsive to at least the m leastsignificant weight digits of said stored code group to produce a secondcontrol signal indicating the position along said segment indicated bysaid first control signal, where m is an integer less than n; andweighting circuit means coupled to said pedestal signal generator meansand said complementary signal generator means operated responsive tosaid first control signals to produce a first voltage equal to saidlower value of voltage of said segment indicated by said first controlsignal, operated responsive to said second control signals to produce asecond voltage corresponding to said position indicated by said secondcontrol signal, and operated to sum said first and second voltages toproduce an output analog voltage represented by said stored digital codegroup.

2. A decoder according to claim 1 wherein said register means includes nbistable devices each storing a digit of said stored code group andhaving a 1 output and a 0 output; said zone decoder means coupled toboth said 1 output and said 0 output of said bistable devices storingsaid x most significant weight digits of said stored code group; saidpedestal signal generator means coupled to said 1 output of saidbistable devices storing said x most significant weight digits of saidstored code group; and said complementary generator means coupled tosaid 1 output of said bistable devices storing said In least significantweight digits of said stored code group.

3. A decoder according to claim 2 wherein said weighting circuit meansincludes a plurality of current generators, a weighting and summingmeans having a plurality of current injection points, each of saidcurrent injection points coupled to appropriate ones of said currentgenerators, and logic circuit means coupled to control said currentgenerators responsive to said first and second control signals toactivate appropriate ones of said current generators to produce saidoutput voltage at the output of said weighting and summing means.

4. A decoder according to claim 3, wherein said weighting and summingmeans includes a ladder attenuator.

5. A decoder according to claim 1, wherein said weighting circuit meansincludes a plurality of current generators, a weighting and summingmeans having a plurality of current injection points each coupled toappropriate ones of said current generators, and logic means coupled tooperate said current generators, responsive to said first and secondcontrol signals to activate appropriate ones of said current generatorsto produce said output voltage at the output of said weighting andsumming means.

6. A decoder according to claim 7, wherein said weighting and summingmeans includes a ladder attenuator.

7. A decoder according to claim 1, wherein n equals seven;

x equals four; and

m equals four.

References Cited UNITED STATES PATENTS 3,290,671 12/1966 Lamoreux340-347 3,298,017 1/1967 Avignon et a1 340-347 3,305,855 2/1967 Kaneko340-347 3,305,857 2/1967 Barber 340-347 3,345,505 10/1967 Schmid 340-347MAYNARD R. WILBUR, Primary Examiner I. GLASSMAN, Primary Examiner

